View PI2EQX5804C_7598489.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ps8926b 06/08/09 block diagram PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis features ? up to 5.0gbps pcie? 2.0 serial redriver? ? supporting 8 differential channels or 4 lanes of pcie interface ? pin strapped and i 2 c con guration controls ? adjustable receiver equalization ? adjustable transmitter amplitude and de-emphasis ? variable input an output termination ? 1:2 channel broadcast ? channel loop-back ? electrical idle fully supported ? receiver detect and individual output control ? single supply voltage, 1.2v 0.05v ? power down modes ? packaging: 100-contact lbga, pb-free & green description pericom semiconductor?s PI2EQX5804C is a low power, pcie? compliant signal redriver?. the device provides programmable equalization, ampli cation, and de-emphasis by using 8 select bits, to optimize performance over a variety of physical mediums by reducing inter-symbol interference. PI2EQX5804C supports eight 100-ohm differential cml data i/o?s between the protocol asic to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user?s platform. the integrated equalization circuitry provides exibility with signal integrity of the pcie signal before the redriver, whereas the integrated de-emphasis circuitry provides exibility with signal integrity of the signal after the redriver. in addition to providing signal re-conditioning, pericom?s PI2EQX5804C also provides power management stand-by mode operated by a power down pin. pin con guration (top-side view) 1 2 3 4 5 6 7 89 10 a vdd b0tx - b0tx+ vdd scl sda vdd b0rx+ b0rx - vdd b a1rx+ gnd gnd a0rx - de_a vdd a0tx - gnd gnd a1tx+ c a1rx - gnd gnd a0rx+ nc pd# a0tx+ gnd gnd a1tx - d vdd b1tx+ b1tx- vdd d2_a vdd b1rx - b1rx+ vdd e sel0_a sel1_a sel2_a d0_a d1_a s0_a rxd_a s1_a sig_a rx50_a f rx50_b sig_b s1_b rxd_b s0_b a1 sel2_b lb# sel1_b sel0_b g vd d a2rx - a2rx+ vdd mode d0_b vdd a2tx+ a2tx - vdd h b2tx+ gnd gnd b3tx - de_b a0 b3rx - gnd gnd b2rx+ j b2tx - gnd gnd b3tx+ reset# d1_b b3rx+ gnd gnd b2rx- k vdd a3rx+ a3rx- vdd d2_b a4 vdd a3tx- a3tx+ vdd nc + ? + ? + ? + ? + ? + ? a b xyrx+ xyrx- xytx+ xytx- xytx- xytx+ xyrx+ xyrx- equalizer equalizer inputleveldetect tocontrollogic output controls output controls inputleveldetect tocontrollogic datalanerepeats4times controlregisters &logic power management i 2 ccontrol sely_x sy_x dy_x de_x pd# sda scl mode lb# res_x rxd_x ax 09-0001
2 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis pin # pin name type description data signals c4 b4 a0rx+, a0rx- i i cml inputs for channel a0, with internal 50-ohm pull down during normal operation, and >200k-ohm otherwise. c7 b7 a0tx+, a0tx- o o cml outputs for channel a0, with internal 50-ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. b1 c1 a1rx+, a1rx- i i cml inputs for channel a1, with internal 50-ohm pull down during normal operation, and >200k-ohm otherwise. b10 c10 a1tx+, a1tx- o o cml outputs for channel a1, with internal 50-ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. g3 g2 a2rx+, a2rx- i i cml inputs for channel a2, with internal 50-ohm pull down during normal operation, and >200k-ohm otherwise. g8 g9 a2tx+, a2tx- o o cml outputs for channel a2, with internal 50-ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. k2 k3 a3rx+, a3rx- i i cml inputs for channel a3 with internal 50-ohm pull down during normal operation, and >200k-ohm otherwise. k9 k8 a3tx+, a3tx- o o cml outputs for channel a3, with internal 50-ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. a8 a9 b0rx+, b0rx- i i cml inputs for channel b0, with internal 50-ohm pull down during normal operation, and >200k-ohm otherwise. a3 a2 b0tx+, b0tx- o o cml outputs for channel b0, with internal 50-ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. d9 d8 b1rx+, b1rx- i i cml inputs for channel b1, with internal 50-ohm pull down during normal operation, and >200k-ohm otherwise. d2 d3 b1tx+, b1tx- o o cml outputs for channel b1, with internal 50-ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. h10 j10 b2rx+, b2rx- i i cml inputs for channel b2, with internal 50-ohm pull down during normal operation, and >200k-ohm otherwise. h1 j1 b2tx+, b2tx- o o cml outputs for channel b2, with internal 50-ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. j7 h7 b3rx+, b3rx- i i cml inputs for channel b3, with internal 50-ohm pull down during normal operation, and >200k-ohm otherwise. j4 h4 b3tx+, b3tx- o o cml outputs for channel b3, with internal 50-ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. control signals h6, f6, k6 a0, a1, a4 i i 2 c programmable address bit a0, a1 and a4. e4, e5, d5 d[0:2]_a i selection pins for channel ax emphasis (see emphasis con guration table) w/ 100k-ohm internal pull up g6, j6, k5 d[0:2]_b i selection pins for channel bx emphasis (see emphasis con guration table) w/ 100k-ohm internal pull up b5 de_a i de-emphasis enable input for channel a0, a1, a2 and a3 with internal 100k- ohm pull-up resistor. set high selects output de-emphasis and set low selects output pre-emphasis. 09-0001
3 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis pin # pin name type description h5 de_b i de-emphasis enable input for channel b0, b1, b2 and b3 with internal 100k- ohm pull-up resistor. set high selects output de-emphasis and set low selects output pre-emphasis. f8 lb# i input with internal 100k-ohm pull-up resistor. lb# = high or open for normal operation. lb# = low for loopback connection of a_rx to a_tx and b_tx. g5 mode i input switch between pin control and i 2 c control with internal 100k-ohm pull-up resistor. a lvcmos high level selects input pin control, and disables i 2 c opera- tion. note, during startup, input status of the control pin (lb#, reset#, pd#, rxd_a/b, sel0-2_a/b, d0-2_a/b, s0-1_a/b, de_a/b) will be latched to the initial state of some i 2 c control pins only once. c6 pd# i input with internal 100k-ohm pull-up resistor, pd# =high or open is normal operation, pd# =low disable the ic, and set ic to power down mode, both input and output go hi-z. d6 nc no connect c5 nc no connect j5 reset# i reset# is an active low channel reset input for channel a0, b0, a1, b1, a2, b2, a3 and b3 with internal 100k-ohm pull-up resistor. when low, the receiver detection cycle is reset, and normal detection cycle is started after the pin goes high. e10 rx50_a o receiver detect output pin for channel a0. rx50_a=high indicates that a 50-ohm termination was sensed at the a0tx+/- outputs. f1 rx50_b o receiver detect output pin for channel b0. rx50_b=high indicates that a 50-ohm termination was sensed at the b0tx+/- outputs. e7 rxd_a i receiver detect enable input for channel a0, a1, a2 and a3 with internal 100k- ohm pull-up resistor. f4 rxd_b i receiver detect enable input for channel b0, b1, b2 and b3 with internal 100k- ohm pull-up resistor. e6, e8 s[0:1]_a i selection pins for channel ax output level (see output swing con guration table) w/ 100k-ohm internal pull up f5, f3 s[0:1]_b i selection pins for channel bx output level (see output swing con guration table) w/ 100k-ohm internal pull up a5 scl i/o i 2 c scl clock input. a6 sda i/o i 2 c sda data input. e1, e2, e3 sel[0:2]_a i selection pins for channel ax equalization (see equalizer con guration table) w/ 100k-ohm internal pull up 09-0001
4 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis pin # pin name type description f10, f9, f7 sel[0:2]_b i selection pins for channel bx equalization (see equalizer con guration table) w/ 100k-ohm internal pull up e9 sig_a o signal detect output pin for channel a0. sig_a=high represents a input signal > threshold at the differential inputs. f2 sig_b o signal detect output pin for channel b0. sig_b=high represents a input signal > threshold at the differential inputs. power pins b2, b3, b8, b9, c2, c3, c8, c9, h2, h3, h8, h9, j2, j3, j8, j9 gnd pwr supply ground a1, a4, a7, a10, b6, d1, d4, d7, d10, g1, g4, g7, g10, k1, k4, k7, k10 v dd pwr 1.2v supply voltage description of operation con guration modes device con guration can be performed in two ways depending on the state of the mode input. mode de- termines whether ic con guration status is from the input pins or via i 2 c control. when mode is set high, the con guration input pins set the con guration operating state as stored in con guration registers. while mode is set high, changes to these control registers are disabled and the initial condition is protected from any changes to insuring a known operating state. when the mode pin is low, reprogramming of these control registers via i 2 c is allowed. note that the mode pin is not latched, and is always active to enable or disable i 2 c access. during initial power-on, the value at the con guration input pins: lb#, reset#, pd#, rxd_a and rxd_b, de_a, de_b, sel0_a, sel1_a, sel2_a, d0_a, d1_a, d2_a, s0_a, s1_a, sel0_b, sel1_b, sel2_b, d0_b, d1_b, d2_b, s0_b, s1_b, will be latched to the con guration registers as initial startup states. 09-0001
5 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis equalizer con guration the PI2EQX5804C input equalizer compensates for signal attenuation and inter-symbol interference (isi) re- sulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high- frequency signal components. because either too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application. equalizer con guration is performed in two ways determined by the state of the mode pin. when the device rst powers up, the selx_[a:b] input pins are read into the appropriate control registers to set the equalization characteristic. if the mode pin is low, reprogramming of these control registers via i 2 c is allowed. each group of four channels, a and b, has separate equalization control, and all four channels within the group are assigned the same con guration state. the equalizer selection table below describes pin strapping options and associated operation of the equalizer. refer to the section on i 2 c programming for information on soft- ware con guration of the equalizer. equalizer selection sel2_[a:b] sel1_[a:b] sel0_[a:b] @1.25ghz @2.5ghz 0 0 0 0.5db 1.2db 0 0 1 0.6db 1.5db 0 1 0 1.0db 2.6db 0 1 1 1.9db 4.3db 1 0 0 2.8db 5.8db 1 0 1 3.6db 7.1db 1 1 0 5.0db 9.0db 1 1 1 7.7db 12.3db output con guration the PI2EQX5804C provides exible output strength and emphasis controls to provide the optimum signal to pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean eye open- ing. control of output con guration is grouped for the a and b channels, so that each channel within the group has the same setting. output con guration is performed in two ways depending on the state of the mode pin. when the device rst powers up, the sx_[a:b], and dx_[a:b] input pins are read into the appropriate control registers to set the power-on state. if the mode pin is low, reprogramming of these control registers via i 2 c is allowed. the output swing control table shows available con guration settings for output level control, as speci ed using the sx_y pins and registers. 09-0001
6 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis output swing control s1_[a:b] s0_[a:b] swing (diff. vpp) 001 v 0 1 0.5v 1 0 0.7v 1 1 0.9v output de-emphasis adjustment d2_[a:b] d1_[a:b] d0_[a:b] de-emphasis 0000 d b 0 0 1 -2.5db 0 1 0 -3.5db 0 1 1 -4.5db 1 0 0 -5.5db 1 0 1 -6.5db 1 1 0 -7.5db 1 1 1 -8.5db emphasis settings are determined by the state of the dex_y input pins and con guration registers, as shown in the output de-emphasis table below. de-emphasis is selected as the default power-on mode in following the pci express speci cation, but can be changed to pre-emphasis via reprogramming the loopback and empha- sis control register using the i 2 c interface. input level detect an input level detect and output squelch function is provided on each channel to eliminate re-transmission of input noise. a continuous signal level below the v th- threshold causes the output driver to go to a high-impre- dance state, so that both the positive and negative output signal are pulled to v dd by the internal pull-up resis- tors. this feature supports the l0s pci express electrical idle state. receiver detect automatic receiver detection is a feature that can set the number of active channels. by sensing the presence of a load device on the output, the channel can be automatically enabled for operation. this allows the PI2EQX5804C to con g- ure itself properly depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card. receiver detect is enabled by the rxd_a, or rxd_b pins, or alternatively via i 2 c programming. when rxd_a or rxd_b is set to low, then the receiver detect operation for that group of channel is disabled, and those channels go directly to 50-ohm input termination to ground and 50-ohm output termination to v dd (for a valid differential channel input level) or to 2k-ohm (if the signal level is less than the threshold level). (continued) 09-0001
7 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis the reset# input is used to reset the receiver detect state machine to its initial state. the start of the receiver detect cycle starts when reset# transitions from low to high. when a receiver detect cycle is begins the differential channel pins are enabled with a 2k-ohm pullup to v dd . a 50- ohm receiver termination will change the pin level. this pin level is evaluated after a xed time-out, and the channel is then set into the proper operating state. the output signals rx50_a and rx50_b represent the receiver detect result for their speci c channels. the i/o operation table summaries the relationships and operation of receiver detect and other signals involved with i/o control. table 4 - i/o operation control control inputs detection states data channel i/o pd# rxd_x reset# rx50 sig_x input termination output termination mode 0 x x x x hi-z hi-z full ic power down, all channels dis- abled 1 0 0 x x hi-z 2k-ohm pull-up channel disabled, output pulls to v dd . receiver detect reset 10 1 x 0 50-ohm pull- down 2k-ohm pull-up channel enabled, no input signal, output pulls to v dd . receiver detect disabled 10 1 x 1 50-ohm pull- down 50-ohm pull-up channel enabled, valid input signal detected, output driving. receiver detect disabled. 1 1 0 x x hi-z 2k-ohm pull-up channel disabled. receiver detect reset. 1 1 1 0 x hi-z 2k-ohm pull-up channel disabled, output pulls to v dd . receiver detect enabled, no receiver detected. 11 1 1 0 50-ohm pull- down 2k-ohm pull-up channel inactive, output pulls to v dd . receiver detect enabled, receiver de- tected. no input signal 11 1 1 1 50-ohm pull- down 50-ohm pull-up channel active, valid input signal de- tected, output driving. receiver detect enabled, load detected. 09-0001
8 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis loopback operation each lane of the PI2EQX5804C provides a loopback mode for test purposes which is controlled by a strapping pin and i 2 c register bit. the lb# pin controls all lanes together. when this pin is high normal data mode is en- abled. when lb# is low the loopback mode is enabled. the gure below diagrams this operation. loopback is not intended to be dynamically switched, and the normal system application is to initialize to one con gura- tion or the other. the loopback mode can also support mux/demux operation. using i 2 c con guration, unused inputs and out- puts can be disabled to minimize power and unnecessary noise. a0 b0 a0 b0 mux function solid: lb_a0b0#=1 dashed: lb_a0b0#=0 a0 b0 a0 b0 demux function solid: lb=1 dashed: lb=0 a0 b0 a0 b0 a0 b0 a0 b0 normal operation loopback mode a0 b0 a0 b0 a0 b0 a0 b0 a0 b0 a0 b0 a0 b0 a0 b0 lb#=1 lb#=0 odis_ao = 1 indis_bo = 1 loopback modes 09-0001
9 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis i 2 c operation the integrated i 2 c interface operates as a slave device, supporting standard rate operation of 100kbps, with 7-bit addressing mode. the data byte format is 8 bit bytes. the bytes must be accessed in sequential order from the lowest to the highest byte with the ability to stop after any complete byte has been transferred. ad- dress bits a4, a1 and a0 are programmable to support multiple chips environment. the data is loaded until a stop sequence is issued. con guration register summary byte mnemonic function 0 sig signal detect, indicates valid input signal level 1 rx50 receiver detect output, indicates whether a receiver load was detected 2 lbec loopback and emphasis control, provides for control of the loopback function and emphasis mode (pre- emphasis or de-emphasis) 3 indis channel input disable, controls whether s channels input buffer is enabled or disabled 4 outdis channel output disable: controls whether a channels output buffer is enabled or disabled 5 reset channel reset 6 pwr power down control, enables power down for each channel individually 7 rxde receiver detect enable, controls the receiver detect operation 8 aeoc a-channels equalizer and output control 9 aeoc b-channels equalizer and output control 10 rsvd reserved 11 rsvd reserved 3.3v to 1.2v bi-directional level shifter if the i 2 c controller is 3.3v bus, the bi-directional level shifter is used to interconnect two sections of an i 2 c- bus system, each section with a different supply voltage and different logic levels. in the bus system of figure 2 the left section has pull-up resistors and devices connected to a 1.2 volt supply voltage, the right section has pull-up resistors and devices connected to a 3.3 volt supply voltage. the devices of each section have i/o?s with supply voltage related logic input levels and an open drain output con guration. the level shifter for each bus line is identical and consists of one discrete n-channel enhancement mos-fet, t1 for the serial data line sda and t2 for the serial clock line scl. the gates (g) has to be connected to the lowest supply voltage vdd1 (1.2v), the sources (s) to the bus lines of the ?lower voltage? section, and the drains (d) to the bus lines of the ?higher voltage? section. the diode between the drain (d) and substrate is inside the mos-fet present as n-p junction of drain and substrate. 09-0001
10 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis the mos-fet?s. the requirements for the most important characteristics of the mos-fet?s, used as bi-directional level shifter. type : n-channel enhancement mode mos-fet. gate threshold voltage : vgs(th) min. 0.8v max. 1.5v on resistance : rds(on) max. 30 ohm @ id= 3ma, vgs= 2.5v input capacitance : ciss max. 50 pf @ vds= 1v, vgs = 0v switching times : ton toff max. 50 ns. allowed drain current : id 30 ma or higher. vdd2= 3.3 v 27k 10k vbias = 2.4v vdd2= 3.3 v 100nf 10k 10k 2sk3018 4.7k 4.7k sda 2 scl 2 g s t1 d g s t2 d 2sk3018 PI2EQX5804C PI2EQX5804C vdd1= 1.2v to i2c controller ?lower voltage? section ?higher voltage? section figure 2. bi-directional level shifter circuit mos-fet? s in table 1 are suitable to be used as level shifter. the 2sk3018 are low cost devices and have good properties for 1.2v/3.3v level shifting, isolation and protection. manufacturer part number manufac- turer drain to source volt- age (vds) current - con- tinuous drain (id) @ 25 c input capac- itance (ciss) @ vds gate threshold voltage package / case 2sk3018t106 rohm 30v 100ma 13pf @ 5v 0.8~1.5v @100 a sot-23 09-0001
11 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis transferring data every byte put on the sda line must be 8-bits long. each byte has to be followed by an acknowledge bit. data is transferred with the most signi cant bit (msb) rst (see the i 2 c data transfer diagram). the PI2EQX5804C will never hold the clock line scl low to force the master into a wait state. note: byte-write and byte-read transfers have a xed offset of 0x00, because of the very small number of con- guration bytes. an offset byte presented by a host to the PI2EQX5804C is not used. addressing up to eight PI2EQX5804C devices can be connected to a single i 2 c bus. the PI2EQX5804C supports 7-bit addressing, with the lsb indicating either a read or write operation. the address for a speci c device is deter- mined by the a0, a1 and a4 input pins. address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 program 0 0 programmable 1=r, 0=w acknowledge data transfer with acknowledge is required from the master. when the master releases the sda line (high) during the acknowledge clock pulse, the PI2EQX5804C will pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse as indicated in the i 2 c data transfer diagram. the PI2EQX5804C will generate an acknowledge after each byte has been received. data transfer a data transfer cycle begins with the master issuing a start bit. after recognizing a start bit, the PI2EQX5804C will watch the next byte of information for a match with its address setting. when a match is found it will respond with a read or write of data on the following clocks. each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop bit. for a write cycle, the rst data byte fol- lowing the address byte is a dummy or ll byte that is not used by the PI2EQX5804C. this byte is provided to provided compatibility with systems implementing 10-bit addressing. data is transferred with the most signi cant bit (msb) rst. after each block write, address pointer will reset to byte 0. 09-0001
12 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis register description byte 0 - signal detect (sig) sig_xy=0=low input signal, sig_xy=1=valid input signal b i t76543210 name sig_a0 sig_b0 sig_a1 sig_b1 sig_a2 sig_b2 sig_a3 sig_b3 t y p errrrrrrr power-on state xxxxxxxx note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the signal detect register provides information on the instantaneous status of the channel input from the input level threshold detect circuit. if the input level falls below the vth- level the relevant sig_xy bit will be 0, indicating a low- level noise or electrical idle input, resulting in the outputs going to the high-impedance off state or squelch mode. if the input level is above vth-, then sig_xy is 1, indicating a valid input signal, and active signal recovery operation. byte 1 - receiver detect output register (rx50) lb_xyxy#=0=loopback mode, lb_xyxy#=1=normal mode, de_x=0=pre-emphasis, de_x=1=de-emphasis b i t76543210 name rx50_a0 rx50_b0 rx50_a1 rx50_b1 rx50_a2 rx50_b2 rx50_a3 rx50_b3 t y p errrrrrrr power-on state xxxxxxxx note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the rx50_xy bits report the result of a receiver detection cycle. one bit is assigned for each channel of the device. rx50_xy is at a logic 1 level indicating a load and receiver was detected. when rx50_xy is 0 then a load device was not detected. the rx50 register is read-only, and is unde ned after power-up until a receiver detection cycle com- pletes. byte 2 - loopback and emphasis control register (lbec) lb_xyxy#=0=loopback mode, lb_xyxy#=1=normal mode, de_x=0=pre-emphasis, de_x=1=de-emphasis b i t76543210 name lb_a0b0# lb_a1b1# lb_a2b2# lb_a3b3# de_a de_b rsvd rsvd type r/w r/w r/w r/w r/w r/w r r power-on state lb# lb# lb# lb# de_a de_b x x note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use individual control for each lane is provided for the loopback function via this register. 09-0001
13 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis byte 3 - channel input disable (indis) indis_xy=0=enable input, indis_xy=1=disable input b i t76543210 name indis_a0 indis_b0 indis_a1 indis_b1 indis_a2 indis_b2 indis_a3 indis_b3 type r/w r/w r/w r/w r/w r/w r/w r/w power-on state 00000000 note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the channel input disable register, provides control over the input buffer of each channel independently. when and indis_xy bit is logic 1, then the input buffer is switched off and the input termination is high im- pedance. this feature can be used for pcb testing, and when only one input is used during loopback as a de- mux function. when indis_xy is at a logic 0 state then the input buffer is enabled (normal operating mode). byte 4 - channel output disable (outdis) odis_xy=0=enable output, odis_xy=1=disable output b i t76543210 name odis_a0 odis_b0 odis_a1 odis_b1 odis_a2 odis_b2 odis_a3 odis_b3 type r/w r/w r/w r/w r/w r/w r/w r/w power-on state 00000000 note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the channel output disable register, allows control over the output buffer of each channel independently. when and outdis_xy bit is logic 1, then the output buffer is switched off and the termination is high imped- ance. this feature can be used for pcb testing, and when only one output is used during loopback as a mux function. when indis_xy is at a logic 0 state then the input buffer is enabled (normal operating mode). byte 5 - channel reset (reset) res_xy# =0=reset, res_xy# =1=normal operation. latch from reset# input at startup b i t76543210 name res_a0# res_b0# res_a1# res_b1# res_a2# res_b2# res_a3# res_b3# type r/w r/w r/w r/w r/w r/w r/w r/w power-on state reset# reset# reset# reset# reset# reset# reset# reset# note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the channel reset register allows for restart of an individual channels receiver detect function. a transition from 0 to 1 initiates a new receiver detect cycle (if the channel is enabled and receiver detect is enabled). while static at 0 or 1, the res_zy# bit will have no effect on operation. the channel reset bits are read/write allowing the current state to be checked. 09-0001
14 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis byte 6 - power down control (pwr) pd_xy# =0=channel off/power down, pd_xy# =1=normal operation, latch from pd# input at startup b i t76543210 name pd_a0# pd_b0# pd_a1# pd_b1# pd_a2# pd_b2# pd_a3# pd_b3# type r/w r/w r/w r/w r/w r/w r/w r/w power-on state pd# pd# pd# pd# pd# pd# pd# pd# note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the power down control register allows for individual control over each channel for power savings. when pd_xy# is logic 0 the channel is turned off. when pd_xy# is 1 then the channel is enabled for normal operation. byte 7 - receiver detect enable (rxd) rxd_xy =0=channel off/power down, rxd_xy =1=normal operation, latch from pd# input at startup b i t76543210 name rxd_a0 rxd_b0 rxd_a1 rxd_b1 rxd_a2 rxd_b2 rxd_a3 rxd_b3 type r/w r/w r/w r/w r/w r/w r/w r/w power-on state rxd_a rxd_b rxd_a rxd_b rxd_a rxd_b rxd_a rxd_b note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the receiver detect enable register allows for control of the receiver detect state machine for each individual channel. when rxd_xy is set to 0, then the receiver detect function is disabled. when rxd_xy is logic 1, then the receiver detect state machine is enabled for operation. the initial state of the register bits are deter- mined by the rxd_a and rxd_b input pins during power-up. byte 8 - a-channels equalizer and output control (aeoc) selx_a: equalizer con guration, dx_a: emphasis control, sx_a: output level control (see con guration table) b i t76543210 name sel0_a sel1_a sel2_a d0_a d1_a d2_a s0_a s1_a type r/w r/w r/w r/w r/w r/w r/w r/w power-on state sel0_a sel1_a sel2_a d0_a d1_a d2_a s0_a s1_a note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the a-channels equalizer and output control register is used to control the con guration of the input equal- izer and output emphasis and levels of the four a channels. these register bits are loaded from the input con- guration pins of the same name at power-on. these bits may be changed if the mode# input is set to allow i 2 c con guration. please refer to the tables (1) equalizer con guration, (2) output swing con guration and 09-0001
15 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis (3) output emphasis con guration earlier in this document for setting information. all four a channels get the same con guration settings. byte 9 - b-channels equalizer and output control (beoc) selx_b: equalizer con guration, dx_b: emphasis control, sx_b: output level control (see con guration table) b i t76543210 name sel0_b sel1_b sel2_b d0_b d1_b d2_b s0_b s1_b type r/w r/w r/w r/w r/w r/w r/w r/w power-on state sel0_b sel1_b sel2_b d0_b d1_b d2_b s0_b s1_b note: r=read only, w=write only, r/w=read and write, x=unde ned, rsvd=reserved for future use the b-channels equalizer and output control register is used to control the con guration of the input equal- izer and output emphasis and levels of the four b channels. these register bits are loaded from the input con- guration pins of the same name at power-on. these bits may be changed if the mode# input is set to allow i 2 c con guration. please refer to the tables (1) equalizer con guration, (2) output swing con guration and (3) output emphasis con guration earlier in this document for setting information. all four b channels get the same con guration settings. byte 10 - reserved byte 11 - reserved reserved bytes 10 and 11 are also visible via the i 2 c interface. these bytes are r/w, are initialized to 0 at power up, are used for ic manufacturing test purposes and should not be changed for normal operation. i c 2 start & stop conditions a high to low transition on the sda line while scl is high indicates a start condition. a low to high transition on the sda line while scl is high de nes a stop condition, as shown in the gure below. 09-0001
16 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis 1.readsequence start r/w ack ack ack noack stop devsel dataout dataoutn ack ack ack datainn datain1 ack ack r/w start stop 2.writesequence 3.combinedsequence dummybyte ack ack r/w start dataout1 ack ack r/w start ack n o dataoutn notes: 1. only block read and block write from the lowest byte are supported for this application. 2. for some i2c application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation. PI2EQX5804C i c master 2 PI2EQX5804C devsel dummy byte devsel devsel PI2EQX5804C i c master 2 PI2EQX5804C i c master 2 i 2 c data transfer 09-0001
17 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) storage temperature ...................................... ?65c to +150c supply voltage to ground potential........ ?0.5v to +2.5v dc sig voltage....................................... ?0.5v to v dd +0.5v current output ........................................ ?25ma to +25ma power dissipation continuous ............... 1w operating temperature............................ 0 to +70c esd, hbm: i 2 c pins............................... ?1kv to +1kv esd, hbm: all other pins....................... ?2kv to +2kv note: stresses greater than those listed under maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and function al operation of the device at these or any other condi- tions above those indicated in the operational sections of this speci cation is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. ac/dc electrical characteristics power supply characteristics (v dd = 1.2 0.05v, t a = 0 to 70c) symbol parameter conditions min. typ. max. units i ddactive power supply current - active all channels switching 800 ma i ddstandby power supply current - standby pd# = 0 5 10 ma i dd-channel power supply current - per channel, active 50 ma ac performance characteristics (v dd = 1.2 0.05v, t a = 0 to 70c) symbol parameter conditions min. typ. max. units t pd channel latency from input to output 750 ps cml receiver input (v dd = 1.2 0.05v, t a = 0 to 70c) symbol parameter conditions min. typ. max. units zrx-diff-dc dc differential input impedance 80 100 120 ohms zrx-dc dc input impedance 40 50 60 ohms vrx-diffp-p differential input peak-to-peak voltage 0.120 1.200 v vrx-cm-acp ac peak common mode input voltage 150 mv vth- signal detect threshold voltage 100 150 mv 09-0001
18 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis equalizer symbol parameter conditions min. typ. max. units j rs-t residual jitter total 0.3 ulp-p j rs-d residual jitter deterministic 0.2 ulp-p j rm random jitter note 2 1.5 psrms notes 1. k28.7 pattern is applied differentially at point a as shown in ac test circuit (see gure). 2. total jitter does not include the signal source jitter. total jitter (tj) = (14.1 rj + dj) where rj is random rms jitter and dj is maximum deterministic jitter. signal source is a k28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and k28.7 (00 11111000) or equivalent for random jitter test. residual jitter is that which remains after equalizing media-induced losses of the environment of figure 1 or its equivalent. the deterministic jitter at point b must be from media-induced loss, and not from clock source modulation. jitter is measured at 0v at point c of the ac test circuit (see gure). cml transmitter output (vdd = 1.2v 0.05v, t a = 0 to 70c) symbol parameter conditions min. typ. max. units z out output resistance single ended 40 50 60 ohms z tx-diff-dc dc differential tx imped- ance 80 100 120 ohms v diffp output voltage swing, dif- ferential |vtx-d+ - vtx-d-| 200 800 mvp-p v tx-diffp-p differential peak-to-peak ouput voltage vtx-diffp-p = 2 * | vtx-d+ - vtx-d- | 0.4 1.6 v v tx-c common-mode voltage | vtx-d+ + vtx-d- | / 2 vdd- 0.3 v t f , t r transition time 20% to 80% (3) 150 ps c tx (1) ac coupling capacitor 75 200 nf note: 1. recommended external blocking capacitor. digital i/o dc speci cations (vdd = 1.2v 0.05v, t a = 0 to 70c) symbol parameter conditions min. typ. max. units v ih dc input logic high vdd/2 +0.2 vdd+0.3 v v il dc input logic low -0.3 vdd/2 -0.2 v v oh dc output logic high i oh = 4ma vdd-0.4 v v ol dc output logic low i ol = 4ma 0.4 v v hys hysteresis of schmitt trigger input 0.2 v i ih (1) input high current 100 a i il1 (2) input low current -20 a i il2 (3) input low current -20 a notes: 1. includes input signals a1, a2, a4, dx_[a:b], de_[a:b], lb#, mode#, pd#, reset#, rxd_[a:b], sx_[a:b], scl, sda, sel_x[a:b] 2. for control inputs without pullups: a1, a2, a4, scl, sda 3. control inputs with pull-ups include: dx_[a:b], de_[a:b], lb#, mode#, pd#, reset#, rxd_[a:b], sx_[a:b], sel_x[a:b] 09-0001
19 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis sda and scl i/o for i 2 c-bus (v dd = 1.2 0.05v, t a = 0 to 70c) symbol parameter conditions min. typ. max. units v ih dc input logic high 1.1 vdd+0.3 v v il dc input logic low -0.3 0.7 v v ol dc output logic low i ol = 3ma 0.4 v v hys hysteresis of schmitt trigger input 0.2 v characteristics of the sda and scl bus lines for f/s-mode i 2 c-bus devices (1) symbol parameter conditions min. typ. max. unit f scl scl clock frequency 0 100 khz t hd;sta hold time (repeated) start condition. after this period, the rst clock pulse is generated 4.0 ? s t low low period of the scl clock 4.7 ? s t high high period of the scl clock 4.0 ? s t su;sta set-up time for a repeated start condition 4.7 ? s t hd;dat data hold time 5.0 ? s t su;dat data set-up time 250 ? ns t r rise time of both sda and scl signals ? 100 ns t f fall time of both sda and scl signals 300 ns t su;sto set-up time for stop condition 4.0 ? s t buf buss free time between a stop and stop condition 4.7 ? s c b capacitive load for each bus line ? 400 pf notes: 1. all values referred to v ihmin and v ilmax levels. 2. a device must initially provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the unde- ned region of the falling edge of scl. 09-0001
20 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis sda scl t f s t hd;sta t low t hd;dat t su;dat high t su;sta t hd;sta sr t su;sto p s t f t r t buf start stop start i 2 c timing channel latency, 5.0 gbps 09-0001
21 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis output level settings (1v left, and 0.5v right at 5.0 gbps) 0.0 db (dx = 000) ?3.5 db (dx = 010) ?6.5 db (dx = 101) ?8.5 db (dx = 111) output de-emphasis characteristics 09-0001
22 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis eye diagrams 5.0gbps (input left, output right) data waveforms, 2.5gbps (left) & 5.0gbps (right) ab c fr4 signal source sma connector sma connector 30 in in out d.u.t. ac test circuit referenced in the electrical characteristic table 09-0001
23 ps8926b 06/08/09 PI2EQX5804C 5.0gbps 4-lane pcie? 2.0 redriver? with equalization & emphasis packaging mechanical: 100-ball lbga (nj) 1 : 100-ball low profile ball grid array (lbga) noitpircsed :edoc egakcap 2055 -dp :# lortnoc tnemucod b :noisiver 80/82/40 :etad nj100 08-0178 ordering information ordering number package code package description PI2EQX5804Cnje nj pb-free & green 100-contact lbga notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? x suf t x = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com redriver is a trademark of pericom semiconductor. pcie ? , and the pci express design mark ? are trademarks of pci-sig ? (www.pcisig.com) 09-0001

▲Up To Search▲

Price & Availability of PI2EQX5804C

	To Download PI2EQX5804C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .